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Logic Based Verification of Software Product Line Feature Model

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dc.contributor.author Hossain, Md. Mosarrof
dc.date.accessioned 2016-11-14T04:15:07Z
dc.date.available 2016-11-14T04:15:07Z
dc.date.issued 5/21/2016
dc.identifier.uri http://dspace.ewubd.edu/handle/2525/1944
dc.description This thesis submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering of East West University, Dhaka, Bangladesh en_US
dc.description.abstract Formal verification of variant requirements has gained much interest in the software product line (SPL) community. Feature diagrams are widely used to model product line variants. However, there is a lack of precisely defined formal notation for representing and verifying such models. This report presents an approach to analyzing SPL variant feature diagrams using first-order logic. The logical representation provides a precise and rigorous formal interpretation of the feature diagrams. Logical expressions can be built by modeling variants and their dependencies by using propositional connectives. These expressions can then be validated by any suitable verification tool such as Alloy. A case study of a Computer Aided Dispatch (CAD) system variant feature model is presented to illustrate the analysis and verification process. en_US
dc.language.iso en_US en_US
dc.publisher East West University en_US
dc.relation.ispartofseries ;CSE00030
dc.subject Logic Based Verification of Software en_US
dc.title Logic Based Verification of Software Product Line Feature Model en_US
dc.type Thesis en_US


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